Circuit Decompositions and Scheduling for Neutral Atom Devices with Limited Local Addressability

Nottingham, Natalia, Perlin, Michael A., Shah, Dhirpal, White, Ryan, et al. · 2024 · 2024 IEEE International Conference on Quantum Computing and Engineering (QCE)

| 编号 NA020 | 主题 编译、布局与调度 | DOI 10.1109/qce60285.2024.00105 |

摘要

摘要保留原文（英文）

摘要取自 arXiv / 出版方元数据，未作翻译，以保证与原文一致。

2024 · 2024 IEEE International Conference on Quantum Computing and Engineering (QCE) Despite major ongoing advancements in neutral atom hardware technology, there remains limited work in systems-level software tailored to overcoming the challenges of neutral atom quantum computers. In particular, most current neutral atom architectures do not natively support local addressing of single-qubit rotations about an axis in the xy-plane of the Bloch sphere. Instead, these are executed via global beams applied simultaneously to all qubits. While previous neutral atom experimental work has used straightforward synthesis methods to convert short sequences of operations into this native gate set, these methods cannot be incorporated into a systems-level framework nor applied to entire circuits without imposing impractical amounts of serialization. Without sufficient compiler optimizations, decompositions involving global gates will significantly increase circuit depth, gate count, and accumulation of errors. No prior compiler work has addressed this, and adapting existing compilers to solve this problem is nontrivial. In this paper, we present an optimized compiler pipeline that translates an input circuit from an arbitrary gate set into a realistic neutral atom native gate set containing global gates. We focus on decomposition and scheduling passes that minimize the final circuit’s global gate count and total global rotation amount. As we show, these costs contribute the most to the circuit’s duration and overall error, relative to costs incurred by other gate types. Compared to the unoptimized version of our compiler pipeline, minimizing global gate costs gives up to 4.77x speedup in circuit duration. Compared to the closest prior existing work, we achieve up to 53.8x speedup. For large circuits, we observe a few orders of magnitude improvement in circuit fidelities.

全文共 12 页；文本提取件位于 .extracted/papers/NA020.txt（不随站点发布）。

本站词条在引用该文献时，会以 wikilink（sources/NA020）链接到本页；右侧「反向链接」面板自动列出所有引用它的词条。