T-count Optimized Design of Quantum Integer Multiplication
Edgard Muñoz-Coreas, Himanshu Thapliyal · 2017 · arXiv quant-ph
| 编号 QM004 | 主题 模运算与乘法 | 链接 arXiv:1706.05113 |
摘要
摘要保留原文（英文）
摘要取自 arXiv / 出版方元数据，未作翻译，以保证与原文一致。
Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on Clifford + T gates. An efficient quantum circuit saves quantum hardware resources by reducing the number of T gates without substantially increasing the number of qubits. Recently, the design of a quantum multiplier is presented by Babu [1] which improves the existing works in terms of number of quantum gates, number of qubits, and delay. However, the recent design is not based on fault-tolerant Clifford + T gates. Also, it has large number of qubits and garbage outputs. Therefore, this work presents a T-count optimized quantum circuit for integer multiplication with only qubits and no garbage outputs. The proposed quantum multiplier design saves the T-count by using a novel quantum conditional adder circuit. Also, where one operand to the controlled adder is zero, the conditional adder is replaced with a Toffoli gate array to further save the T gates. To have fair comparison with the recent design by Babu and get an actual estimate of the T-count, it is made garbageless by using Bennett’s garbage removal scheme. The proposed design achieves an average T-count savings of compared to the recent work by Babu. Further, comparison is also performed with other recent works by Lin et. al. [2], and Jayashree et. al.[3]. Average T-count savings of and are achieved compared to the recent works by Lin et. al., and Jayashree et al., respectively.
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